ISE محصولی از کمپانی Xilinx است که یکی از قدرتمند ترین نرم افزار ها برای کار با انواع FPGA به شمار می رود. این نرم افزار قادر به برنامه نویس با زبان هایی مانند Verilog ، VHDL می باشد.

این آموزش تصویری VHDL ، ISE و FPGA را با طراحی یک آلارم خانگی ساده آموزش می دهد. این دوره به معرفی نرم افزار ISE ، کار با ابزار ها و ویژگی های ISE و مبانی الکترونیک دیجیتال می پردازد. در ادامه نحوه کدنویسی VHDL ، استفاده از FPGA ، شبیه سازی و پیکربندی FPGA را می آموزید.
این دوره آموزشی محصول موسسه Udemy است.

سرفصل های دوره:

  • مقدمه ای بر FPGA
  • مشاهده منابع در FPGA
  • دانلود و نصب ISE Webpack
  • کار با رابط کاربری گرافیکی ISE
  • نحوه راه اندازی FPGA
  • کار با انواع داده ها
  • کار با اپراتورها
  • نحوه کدنویسی با VHDL
  • کار با گیت های XOR/NOR
  • نحوه طراحی بردارها
  • طراحی مدارهای سنکرون
  • طراحی فلیپ فلاپ
  • کار با ثابتها و متغیرها
  • کار با آرایه ها
  • کار با حلقه ها
  • کار با توابع
  • ویرایش فرآیند همگام سازی
  • نحوه رمزگشایی مدار
  • کار با مدار Debouncer
  • مقدمه ای بر شبیه سازی
  • شبیه سازی ISIM
  • نحوه پیاده سازی  مدار
  • نحوه تست مدار
  • و…

عنوان دوره: Udemy Learn VHDL, ISE and FPGA by Designing a basic Home Alarm
سطح: متوسط
مدت زمان: 6 ساعت
نویسنده:M Ajmir GOOLAM HOSSEN

توضیحات:

In 6 hours, you will become comfortable with designing in VHDL using ISE tools and test your design on a Basys2 board
This course was designed to equip you with the knowledge and skill that will get you up to speed with FPGA Design in VHDL. You will be expected to have some basic knowledge on digital electronics such as the meaning of Flip Flops, Gates and Finite State Machine, and also some basics of programming language would help in the course.
Although the design flow will be dealt with in almost its entirety, the course starts from the basics and take you up to an intermediate level, where you will be able to take a design from a concept through the different stages of design until seeing the design work on a board.
The course is structured in four parts, starting with a simplistic view at how FPGA's work and the resources that are available on a typical FPGA. The tool FPGA Editor will be used. Then an overview of ISE Flow will be presented in part 2, along with demos on how the tool is downloaded, installed and used. The third part of the course will explain and demonstrate how the most useful VHDL syntaxes are written, and at each step, the Technology Schematic is viewed to understand how VHDL codes are synthesized into logic.
The last part is about designing a Home Alarm System from the concept and State Diagram. A step-by-step approach is used to show all the stages of the flow, including writing of the codes, Synthesize, add constraints, run Implementation, Timing Analysis, Behavioural Simulation and Post implementation Simulation and Configuration of the FPGA and PROM on a Basys 2 board.
The course consists of 6 hours of videos, spread over 50 lectures, and provide demos to show how the tool is used effectively.
What are the requirements?
Basic understanding of programming
Basics of Digital Electronics
What am I going to get from this course?
Over 57 lectures and 6 hours of content!
Write VHDL Codes
Use FPGA Editor to understand a design and the available resources
Create Testbenches and Run Simulation
Create Timing Constraints
Run Timing Analysis
Add constraints with PlanAhead
View and understand the Technology Schematics after Synthesis
Generate an IP Core
Run Implementation
Extract information from ISE Reports
Solve errors and understand warnings encountered in the ISE flow
Configure the FPGA and ROM with iMPACT
What is the target audience?
The course was designed to help you get started from the basics and rise to an intermediate level
Students
Professionals who want to gain these skills
Electronics Enthusiasts
Research Scientists

Section 1: Overview of the Course
Lecture 1	
The Goals
02:29
Section 2: The Device
Lecture 2	
Introduction to FPGAs 
04:04
Lecture 3	
Look Up Tables 
03:35
Lecture 4	
Resources on the FPGA 
04:31
Lecture 5	
Viewing Resources on FPGA Editor 
06:27
Section 3: The Software
Lecture 6	
The ISE Flow 
05:26
Lecture 7	
Download and Install ISE Webpack 
02:21
Lecture 8	
Get a License for ISE 
02:45
Lecture 9	
The ISE GUI - Project Navigator 
10:43
Lecture 10	
Launching FPGA Editor 
02:01
Section 4: The Language
Lecture 11	
Main parts of VHDL 
07:30
Lecture 12	
Data Types 
08:42
Lecture 13	
Operators 
04:34
Lecture 14	
Synthesize a simple piece of VHDL code 
14:06
Lecture 15	
View RTL and Technology Schematic 
04:34
Lecture 16	
NOT Gate 
04:51
Lecture 17	
AND/OR Gates 
10:26
Lecture 18	
XOR/NOR Gates 
04:31
Lecture 19	
Standard Logic Vector 
05:20
Lecture 20	
A Logic Unit 
03:21
Lecture 21	
Synchronous process 
08:07
Lecture 22	
Synthesis option 
03:13
Lecture 23	
Make a design synchronous 
05:11
Lecture 24	
Language Template and Synthesis of Flip Flop example code 
06:10
Lecture 25	
Block RAM synthesis from Language Template 
03:52
Lecture 26	
Signals, Constants and Variables 
04:05
Lecture 27	
Arrays 
07:56
Lecture 28	
Generics 
07:59
Lecture 29	
Addition and Subtraction 
07:27
Lecture 30	
Multiplication 
07:22
Lecture 31	
Libraries and Packages 
07:28
Lecture 32	
If Statements 
12:19
Lecture 33	
Case Statements 
09:17
Lecture 34	
Loops 
05:32
Lecture 35	
Functions 
06:21
Section 5: An Example
Lecture 36	
Overview of the Alarm System 
04:20
Lecture 37	
The State Diagram 
05:24
Lecture 38	
Finite States Machine Template 
09:07
Lecture 39	
Define the States 
03:26
Lecture 40	
Editing the Sync Process 
09:00
Lecture 41	
Editing the Output Process 
06:34
Lecture 42	
Editing the Next State Decode Process 
12:15
Lecture 43	
Running Check Syntax and Debug syntax errors
04:24
Lecture 44	
Adding alarm output and sensor input 
05:53
Lecture 45	
Add a Debouncer Circuit 
08:10
Lecture 46	
Introduction to Simulation 
04:37
Lecture 47	
Create a Test Bench for Simulation 
11:00
Lecture 48	
Run ISIM Simulation 
04:22
Lecture 49	
Instantiate the Design in a Top Module 
07:06
Lecture 50	
Adding a Digital Clock Manager 
11:31
Lecture 51	
Adding Location Constraints 
06:29
Lecture 52	
Adding Timing Constraints 
03:14
Lecture 53	
Run Implementation 
04:57
Lecture 54	
Run Post Route Simulation 
03:18
Lecture 55	
Timing Analysis 
04:12
Lecture 56	
Generate Programming File 
01:08
Lecture 57	
Load design on Basys 2 Board 
08:14

حجم فایل: 1.7GB